1. Field of the Invention
The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device including a test circuit that generates a test signal to be used for adjustment on operation of an internal circuit.
Priority is claimed on Japanese Patent Application No. 2010-72393, filed Mar. 26, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
As semiconductor devices are shrunken, variations in electric characteristics of the semiconductor devices due to variations of manufacturing thereof have increased. The increased variations of the electric characteristics will increase the need to adjust operations of the internal circuit based on a test result, wherein the test result has been obtained by a test of the internal circuit using a test signal generated by a test circuit included in the semiconductor device. The test circuit generates the test signal for adjustment on operation of the internal circuit. The test signal is used to optimize internal power voltage and internal signal timing. The test circuit generates the test signal to adjust internal power voltage and internal signal timing and reduce operating margin of the internal circuit so as to detect malfunction of a semiconductor device and to determine that the semiconductor device with the smaller margin be defective.
Japanese Unexamined Patent Application, First Publication, No. 2001-243796 discloses a semiconductor device that includes a test circuit generating a plurality of test signals.